Transceiver System Design- Get an A

How to design a transceiver system design

Design a transmitter and receiver to major component level (see note below) to operate to the following specification:

System

1. 2.450GHz carrier frequency
   1. Modulation type at R b/s specified in the table below
   1. Half-duplex operation (transmit or receive, one at a time). Minimum transmission length in any direction is 105 symbols.
   1. Channel Spacing: 2.5R Hz
   1. The design should minimise component complexity and cost for a medium-size production volume of 100k units. (i.e. do not specify general purpose research hardware or the design of custom chipsets)

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Transmitter

• Transmit filtering: 50% rolloff, root raised cosine, implemented in DSP
  • Transmit power: W dBm into 50 ohm antenna load (Compliance matrix entry required, See Section 6)
  • Harmonics of the carrier frequency shall be less than –50dBc (relative to the fundamental frequency transmission power W) (Compliance matrix entry required)

Receiver

• Bit Error Rate (BER) less than 10-3 BER with receiver power input of P dBm. Channel type: Non- dispersive with Additive White Gaussian Noise (AWGN). Simulation performance to be demonstrated and shown in a graph over a BER range from 10-4 to 10-1. (Compliance matrix entry required).
  • Correct demodulation at receiver power up to a maximum signal input power of -50dBm (demodulation must be possible at this input power level). (Receiver linearity requirement) (Compliance matrix entry required)

• Receiver structure: Superheterodyne (final mixing to quadrature IF is permissible) (Compliance matrix entry required)
  • Adjacent channel rejection:
    • 1st channel:30dB min (Compliance matrix entry required)
    • 2nd channel:50dB min (Compliance matrix entry required)
  • Image channel rejection: 50dB min (Compliance matrix entry required)
  • Operation to specification paragraph 3.1 with a maximum carrier frequency error of 1kHz (this specifies the offset in frequency between Tx and Rx. Simulated performance to be tested at offsets of –999Hz, 0Hz,

+999Hz (Note that, for R=20kb/s, the test offsets shall be reduced to +99Hz and -99Hz) (Compliance matrix entry required)

• Receive data filtering, detection and bit timing synchronisation: to be designed for implementation in DSP. DSP processing power (number of million instructions per second (MIPs)) must be justified. (Compliance matrix entry required)

• Bit timing synchronisation, test results to demonstrate operation of synchronisation. Time to lock to sampling point at P dBm input signal: no more than 1,000 symbols. (Compliance matrix entry required)

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Team variations:

Team	A	B	C	D	E	F	G	H	I
R	20k	2M	20M	20k	2M	20M	200k	20M	20M
W	10	20	20	10	20	20	20	10	20
P	-115	-95	-85	-107	-95	-85	-100	-85	-85
Modulation	Pi/4DQPSK	DQPSK	Pi/4DQPSK	8DPSK	Pi/4DQPSK	DQPSK	8PSK	Pi/4DQPSK	DQPSK

Design process:

Carry out a design of the major components to meet the specification (i.e. mixers, filters, amplifier blocks). The choice of each component block should be justified against the specification. Components should be chosen from up-to-date component supplier information.

The DSP sections of the design should be designed as a Matlab simulation using a complex baseband representation (i.e. 0Hz carrier frequency).

The individual report should be no more than 30 pages long, including both transceiver design and OFDM & fOFDM parts, and contain a design discussion, the design, and simulation results.

Note: you do not need to design secondary items (e.g. power supplies, displays, decoupling components, phase locked loop details)

Report content checklist:

Please check that you have correct answers for the following checklist questions:

1. Is the target Eb/No for your modulation scheme correct and understood?

• Have you checked the calculation of the target Noise Figure?

• Have you checked the derivation of the calculated system Noise Figure?

• Does the radio architecture achieve what is required (single RF connection, meets the requirement specification)? It should contain the designs for the parts below:

One or two superhet stages

RF Po

• 

• Do you have a diagram of the system architecture with clearly labeled gain and NF contributions?

• Are all amplifiers clear of saturation under maximum signal power input conditions (-50dBm) unless otherwise intended?

• Do you understand the design of the receiver architecture, even if you were not part of the team that worked on it?

• Do you understand the operation of the software simulation, even if you were not part of the team that worked on it?

• Have you checked through that each item of the specification is addressed in your design?

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Report Structure:

Apart from the personal reflection, write the report as a technical report in the passive style (e.g. “the amplifier was selected for a noise figure of less than …” rather than I selected the amplifier for a noise figure …”)

Please structure your report with the following chapter headings:

1. Introduction (include a list of your team members and the contributions – including yours

– to the assignment)

• Specification adjusted to your team’s requirement, including NF target.
• Radio design
  • Receiver
  • Transmitter
  • DSP Hardware (including A/D and D/A)
• Signal Processing
  • Modulation and demodulation
  • Sampling
  • Bit timing synchronization
  • OFDM and filtered-OFDM
• Simulation Results
  • BER vs Eb/No
    • 0 Hz offset

5.1.2. +Hz offset

5.1.3. -Hz offset

• Results of OFDM
• Compliance matrix.
  • Compliance Table

This should be a table of the specification points above, a column including the spec requirement, plus a column noting your response to each point (e.g. reference to a section number where it is discussed). Also state whether the design is compliant with the specification point, e.g. image rejection 55dB see section 3.1.5). Do not underestimate the time to do this – it should be done as a team at the same time as you perform the design.

For example:

Spec. Para.	Exceeds/Fully/       Partial /Not done	Requirement Value	Achieved Value	See        report section
3.5	Exceeds	50dB	55dB	3.1.5

7.      Personal reflection. Make this brief (less than half a page), cover what you learnt and anything you want to say about the teamwork, assignment, good and bad

• Conclusion
• Acknowledgements (to anyone you want to thank for assistance in completing the assignment)
• References

Process:

1. Choose one of the team members to act as team leader who is responsible for ensuring that the design is organised and nothing is left out. The team leader will organise to report the progress and explain the design issues during the design process.
2. Review your specification and ensure that everyone understands what is meant by each point. Make up a compliance matrix (see Report Structure above) to use as a guide to fill in as the design progresses.
3. Start on the superhet design first, since it is independent from the baseband signal processing. First of all, find suitable filters that will meet your image and adjacent channel rejection and at the same time let the signal through. Start by choosing an IF filter that will meet the specification and then work toward the front end.

Possible vendors are: TDK, Vectron, Murata, NJR, TOKO, Tai-SAW, Sawtek, Golledge. If the filters specs do not allow the design to meet the specification, you may need to think of a double superhet design or a high sampling frequency for the DSP and do the adjacent channel filtering in the DSP.

• Please note that, as in assignment 1, the matched filtering is performed in the DSP operation. Any filtering in the receiver before this point must have a wider frequency response so that the complete cascade of receive filters is dominated by the matched filter.
• In parallel with the filter search, someone can do a noise figure calculation and search out a suitable low- noise amplifier.
• Find a suitable A/D converter and its input signal requirements
• Then specify suitable amplifiers and mixers and oscillators to complete the superhet design. You need to calculate the effect of the circuit noise, and look at the effect of handling the specified large signals (amplifiers overloading, both transmitter and receiver).
• The DSP design is in two parts, the hardware required for it (programmable processor or purpose- bought hardware), and the simulation code. Assign members of the group to these parts but remember that the hardware has to do what the simulation requires. Hint: by far the most intensive signal processing task is the filter. Note – the most of the baseband simulation work can be done in parallel with the receiver architecture design, so start early on it.

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Design Targets:

3 Nov *Identify the S/N (Eb/N_o) for the BER with your modulation scheme and go on to complete Noise Figure calculations, calculating a maximum allowable system noise figure. Have at least a candidate filter for the (final) IF filter.

10 Nov *Finish your search for suitable filters and propose a superhet design

17 Nov *Identify and propose the complete structure of the transmitter and receiver

*Identify individual amplifiers and mixers

24 Nov *Identify the DSP requirements (in terms of MACS – multiplier/accumulations per second) for the transmit/receive functions (note that transmitter and receiver are not operating at the same time, and that the dominating processing requirement will be the matched filter. Propose a suitable DSP implementation (e.g. Programmable DSP or ‘hard wired’ such as in a FPGA – field programmable gate array).

*Propose the detailed changes to the Assignment 1 Matlab code to perform the demodulation required (pay particular attention to the frequency offset)

1 Dec      *Present simulations of demodulation performance including behaviour with frequency offset

The individual report should be not more than 30 pages long (shorter if you can) and contain a design discussion, the design, and simulation results.

1. Be able to design a transceiver system architecture against a comprehensive performance specification.
2. Design and present a simulation of a communication system using computational baseband models.

Criterion	Description	LOs	Total
Transceiver Design	Technical validity of transceiver design	1	30/100
Transceiver Report	Description of superhet transceiver design	1	40/100
Simulation Design	Technical validity of baseband processing	2	30/100

Report section	Criteria for full marks	Usual Marks Distribution
Introduction	Name on report. Clear description of the task, description of team member tasks, including your own contribution	5/100
Specification	Clear statement of your team specification. Clear and correct derivation of the NF target figure and reference to any sources you used for the target Eb/No. Correct calculation of signal bandwidth and its implication for filter choice.	10/100
Radio design	Clear and correct description of the reasons for the choices of frequency plan. A well-labelled and clear diagram showing key details for all blocks (NF, gain, freq, insertion loss, filter rejection achieved, etc.). Clear demonstration that adjacent channel filtering and all image channel rejection requirements are met. Analysis of achieved NF is correct and within specification, with APPCAD table of NF analysis. Clear and correct analysis of overall gain for Tx and Rx chains, including maximum input signal analysis and treatment of any amplifiers in saturation under this condition. Clear and correct transmit harmonic level analysis. Correct analysis of ADC and DAC choice. Correct analysis of DSP choice. Listing of all part numbers used, their key performance aspects for why they were chosen.	30/100
Signal Processing	Clear description of the changes to Assignment 1 Matlab code to implement the symbol encoding and decoding. Clear description of the differential	15/100

	demodulation routine. Clear description of the bit timing recovery routine. Clear description OFDM and filtered-OFDM.
Simulation results	Presentation of performance curves of BER vs Eb/No for zero, positive and negative frequency offsets, all on the same graph. Include curves for beyond-spec frequency offsets to show the degradation in performance. Clear statement of the averaging period used for bit timing recovery. Comments on any unexpected deviations from expected performance. Presentation of simulation results of OFDM and f- OFDM systems.	15/100
Compliance Matrix	Clear statement of compliance/non-compliance and references to report paragraphs. No instances of non- compliance being passed as compliance.	10/100
Personal reflection	A thoughtful reflection covering, at least, lessons learnt, team work experience.	5/100
Conclusion	A concise description of the work and its results	5/100
References	References supported principles/design/analysis/ are listed and appropriately cited	5/100

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